1. Field
Various embodiments relate to a memory system including a memory device and, more particularly, to a memory system capable of repairing a memory device in which an error has occurred, and an operation method thereof.
2. Description of the Related Art
A memory system is applied to various electronic devices for consumers or industry, for example, computers, mobile phones, PDA (Portable Digital Assistants), digital cameras, game machines, navigation systems and the like, and used as a main memory device or secondary memory device. Memory devices constituting the memory system may be divided into volatile memory devices such as DRAM (Dynamic Random Access Memory) and SRAM (Static RAM) and nonvolatile memory devices such as ROM (Read Only Memory), MROM (Mask ROM), PROM (Programmable ROM), EPROM (Erasable Programmable ROM), EEPROM (Electrically Erasable Programmable ROM), FRAM (Ferroelectric RAM), PRAM (Phase-change RAM), MRAM (Magnetoresistive RAM), RRAM (Resistive RAM) and flash memory.
Among the memory devices, DRAM has been continuously scaled down in order to satisfy the demand for a larger memory capacity in smaller chips. To accommodate further increases in capacity and operation speed required by memory systems, multiple DRAMs may be packaged into a memory module and applied to a memory system. For example, a plurality of memory devices may be packaged in the form of a module integrated on a PCB (Printed Circuit Board), and mounted in a PC or the like through a slot. Among the various modules which are applied to various systems, a module in common use is a DIMM (Dual In-line Memory Module). A DIMM which can be used as a main memory in a computing platform may include a plurality of DRAMs mounted and accessed in parallel.
With the development of more advanced memory systems, the number of DRAMs included in one memory module has gradually increased. Furthermore, for faster operations of the memory systems, the plurality of DRAMs included in the memory module may be accessed in parallel to input/output data during one write/read operation. When a memory module is implemented with a multi-rank scheme in which two or more ranks, each having a plurality of DRAMs, are provided, all DRAMs included in the same rank may simultaneously input/output data. That is, data may be written to/read from the DRAMs on a rank basis. Therefore, when an error occurs in any one DRAM included in the memory module during such a write/read operation and the error-occurred DRAM is processed as a failure or chipkill, remaining DRAMs included in the same rank as the error-occurred DRAM cannot normally perform a write/read operation. Therefore, there is a demand for research on a method capable of effectively processing data of DRAM having an error therein in a memory system which operates on a rank basis.